Semiconductor device and manufacturing process thereof

ABSTRACT

In a peripheral circuit region requiring a conductive path between layers at the periphery of a memory cell array region, a conductive path is provided, after removing a silicon nitride film used for self-alignment contact from the area of the contacting portion of a conductor, by forming an interlayer oxide film on the conductor and providing an opening through the interlayer oxide film. Alternatively, a conductive path is provided, after forming the interlayer oxide film on the silicon nitride film used for self-alignment contact, by forming an opening throughout the interlayer oxide film and silicon nitride film.

TECHNICAL FIELD

[0001] The present invention relates to a semiconductor device using aself-alignment contact and a manufacturing process thereof, and moreparticularly to an aluminum contact after a self-alignment contactprocess of a semiconductor device.

BACKGROUND ART

[0002] A conventional semiconductor device using self-alignment contactprocess is first described taking up a dynamic random access memory(DRAM) as an example. FIG. 29 shows a plan view and a cross-sectionalview of a conventional DRAM structure. As shown in FIG. 29, in a memorycell of the DRAM, first transfer gates (word lines: WL) are disposed ona semiconductor substrate, and then bit lines (BL) are further placedthereabove. Therefore, a bit line contact is designed between wordlines, and dropped into a gap between word lines from above.

[0003] On the other hand, with regard to the capacitor, athree-dimensional stack type cell or a trench type cell has beendeveloped instead of the conventional parallel flat plate type electrodethat has reached a limit of capacity. In particular, in the stack type,the COB structure (Capacitor-Over-Bit line) is capable of occupying thefull area of an unit cell as a memory region, regardless of the bit linecontact. Therefore the COB structure has been evaluated again and isbeing employed increasingly (see for example, IDEM Tech. Dig. 1988, pp.592-595). In this structure, as suggested by the name COB, the capacitoris located over the bit line. Therefore a contact of the capacitor,i.e., a storage node contact is to be designed inside the latticesformed by the bit lines and word lines, and the contact has to bedropped into a gap between the lattices from above.

[0004] With the progress of ultra-fine processing technology, it hasbecome increasingly difficult to control the total variation in overlayor dimension to be smaller than the advancing speed of micronization. Ifthere is any deviation in overlay, the bit line contact or storage nodecontact may short-circuit with the transfer gate, as shown in FIG. 29,for example. It is therefore required to establish a process assemblingtechnology, or a self-alignment contact technology having a certainmargin of controllability in lateral direction in the ultra finemanufacturing process.

[0005]FIG. 30 shows an example of self-alignment contact technologyusing a silicon nitride film. In the technology, there are SiN (siliconnitride) film side wall method and a blanket SiN (silicon nitride) filmmethod. In the SiN (silicon nitride) film side wall method (see U.S.Pat. No. 5,270,240, for example), an upper and side surface of a leadline are covered with a nitride film. In the blanket SiN film method(see Symp. VLSI Tech. Dig. 1987, pp. 93-94, for example), a nitride filmis held between interlayer oxide films. In both methods, it is intendedto cover a bottom line serving as a transfer gate with a SiN film whichfunctions as an etching stopper. In the SiN side wall method, an oxidefilm is etched to make a contact with a substrate without cuttingthrough the SiN film. On the other hand, in the blanket SiN method,etching of an oxide film is once stopped at a SiN, and then the SiN andunderlying oxide film are etched to make a contact with the substrate.

[0006] In such a device having an opening in an oxide layer forself-alignment contact with a nitride film as a stopper, there arises aproblem of contact etching for aluminum leads in the later process. FIG.31 shows various states of aluminum contacts provided through aninterlayer insulating film, and indicates that contacts are to be madeat various depths in the interlayer film. As shown in FIG. 31,particularly when an interlayer film for the aluminum contact isflattened, the contact becomes deeper in the active region or on theword line, and aspect ratio becomes large. In the fine contact hole witha large aspect ratio, a RIE Lag (reactive ion etching lag) takes placethereby increasing etching speed in the bottom of the hole. Particularlyin the self-alignment method employing a nitride film as a stopper, ahard-to-etch nitride film is located on the bottom of the deep contacthole where RIE lag is likely to occur. Therefore, over etching orpenetrating may occur in bit line hole or cell plate hole on the upperpart, while an opening in the nitride film is being provided in theother deep hole.

[0007] Thus, in the conventional manufacturing process of asemiconductor device using self-alignment contacts, various problemsexist in the later process of forming an aluminum contact.

DISCLOSURE OF THE INVENTION

[0008] The present invention was made to solve the problems discussedabove, and has an advantage of providing a semiconductor device and amanufacturing process thereof in which a self-alignment contacttechnology is introduced using a silicon nitride film or the like, and aconductive path such as an aluminum contact is effectively formedbetween layers.

[0009] According to one aspect of the present invention, a semiconductordevice includes a semiconductor substrate which has a plurality ofcontact portions on a principal plane. An insulating film is applied tothe principal plane of the semiconductor substrate. A conductive sectionhaving a contact portion is disposed in the insulating film near theprincipal plane of the semiconductor substrate. A silicon nitride filmis disposed in the insulating film for covering the principal plane ofthe semiconductor substrate and the conductive section. A conductivepath is provided through the insulating film and the silicon nitridefilm and extended to the contact portion of the conductive section.

[0010] In another aspect of the present invention, the semiconductordevice further comprises a conductive path provided through theinsulating film and the silicon nitride film, and extended to one of thecontact portions of the semiconductor substrate.

[0011] In another aspect of the present invention, the semiconductordevice further comprises a conductor having a contact portion disposedin the insulating film. Another conductive path is provided through theinsulating film and extended to the contact portion of the conductor.

[0012] The inventions stated above are preferably applied to asemiconductor memory device, in which the conductive section serves as atransfer gate, and the conductor in the insulating film serves as a bitline or a cell plate.

[0013] In another aspect of the present invention, a semiconductordevice includes a semiconductor substrate which has a plurality ofcontact portions on a principal plane. An insulating film is applied tothe principal plane of the semiconductor substrate. A conductive sectionhaving a contact portion is disposed in the insulating film near theprincipal plane of the semiconductor substrate. A conductive sectionhaving a contact portion is disposed in the insulating film near theprincipal plane of the semiconductor substrate. A silicon nitride filmis disposed in the insulating film over and at a surrounding area of atleast one of the contact portions on the principal plane of thesemiconductor substrate and the silicon nitride film is removed in theregion of the other contact portions and the conductive section. Aconductor is disposed in the insulating film, and a conductive path isprovided through the insulating film and the silicon nitride film, andis extended from the conductor to one of the contact portions of thesemiconductor substrate. Another conductive path is provided through theinsulating film and extended to the contact portion of the conductivesection.

[0014] In another aspect of the present invention, the semiconductordevice further comprises a conductive path provided through theinsulating film and extended to the other contact portion of thesemiconductor substrate.

[0015] In another aspect of the present invention, the semiconductordevice further comprises another conductor having a contact portionthereof disposed in the insulating film. Another conductive path isprovided through the insulating film and extended to the contact portionof another conductor.

[0016] The inventions stated above are preferably applied in asemiconductor memory device, in which the conductive section serves as atransfer gate, and the conductor in the insulating film serves as a bitline, and another conductor in the insulating film serves as a bit lineor a cell plate.

[0017] In another aspect of the present invention, a semiconductordevice include a semiconductor substrate which has a plurality ofcontact portions on a principal plane. An insulating film is applied tothe principal plane of the semiconductor substrate. A conductive sectionhaving a contact portion is disposed in the insulating film near theprincipal plane of the semiconductor substrate is projected from theprincipal plane. a silicon nitride film is disposed on a side surface ofthe conductive section in the insulating film. A conductive path isprovided through the insulating film and extended to at least one of thecontact portions of the semiconductor substrate.

[0018] In another aspect of the present invention, the semiconductordevice further comprises a conductive path provided through theinsulating film and extended to at least one of the contact portions ofthe semiconductor substrate.

[0019] In another aspect of the present invention, the semiconductordevice further comprises a conductor having a contact portion thereofdisposed in the insulating film, and another conductive path is providedthrough the insulating film and extended to the contact portion of theconductor.

[0020] In inventions stated above are preferably applied in asemiconductor memory device, in which the conductive section serves as atransfer gate, and the conductor in the insulating film serves as a bitline or a cell plate.

[0021] In another aspect of the present invention, a semiconductordevice includes a semiconductor substrate which has a plurality ofcontact portions on a principal plane. An insulating film is applied tothe principal plane of the semiconductor substrate. A conductive sectionhaving a contact portion is disposed in the insulating film near theprincipal plane of the semiconductor substrate and is projected from theprincipal plane. a silicon nitride film is disposed to cover a surfaceof the conductive section in the insulating film. A conductive path isprovided through the insulating film and the silicon nitride film andextended to the contact portion of the conductive section.

[0022] In another aspect of the present invention, the semiconductordevice further comprises a conductive path provided through theinsulating film and extending to at least one of the contact portions ofthe semiconductor substrate.

[0023] In another aspect of the present invention, the semiconductordevice further comprises a conductor having a contact portion disposedin the insulating film, and another conductive path is provided throughthe insulating film and extended to the contact portion of anotherconductor.

[0024] The inventions stated above are preferably applied in asemiconductor memory device, in which the conductive section serves as atransfer gate, and the conductor in the insulating film serves as a bitline or a cell plate.

[0025] According to another aspect of the present invention, in amanufacturing process of a semiconductor device, a first insulating filmis applied to a principal plane of a semiconductor substrate. Aconductive section is formed on the first insulating film. A secondinsulating film is applied to the conductive section. A silicon nitridefilm is applied to the first and second insulating films. The siliconnitride film is removed at least from a region of the contact portion ofthe conductive section. A third insulating film is applied to the wholesurface. A conductive path is formed through the third insulating filmand is extended to the contact portion of the conductive section.

[0026] In another aspect of the present invention, in a manufacturingprocess of a semiconductor device, a first insulating film is applied toa principal plane of a semiconductor substrate. A conductive sectionhaving a contact portion thereof is formed on the first insulating film.A second insulating film is applied to the conductive section. A siliconnitride film is applied to the first and second insulating films. Thesilicon nitride film is removed leaving at a predetermined portion ofthe principal plane of the semiconductor substrate. The whole surface iscovered with a third insulating film, and a conductive path is formedthrough the third insulting film and extended to the contact portion ofthe conductive section.

[0027] In another aspect of the present invention, in a manufacturingprocess of a semiconductor device, a first insulating film is applied toa principal plane of a semiconductor substrate. A conductive sectionhaving a contact portion thereof is formed on the first insulating film.The conductive section is covered with a second insulating film. Asilicon nitride film is applied to the first and second insulting films.The silicon nitride film is removed leaving at a side surface of theconductive section. The whole surface is covered with a third insulatingfilm, and a conductive path is formed through the third insulating filmand extended to the contact portion of the conductive section.

[0028] In another aspect of the present invention, in a manufacturingprocess of a semiconductor device, a first insulating film is applied toa principal plane of a semiconductor substrate. A conductive sectionhaving a contact portion thereof is formed on the first insulating film.A second insulating film is applied to the conductive section. A siliconnitride film is applied to the first and second insulating films. Athird insulating film is applied to the silicon nitride film. Aconductive path is formed through the third insulating film, the siliconnitride film and the second insulating film and extended to the contactportion of the conductive section.

[0029] In another aspect of the present invention, in a manufacturingprocess of a semiconductor device, further a conductor having a contactportion is embedded in the third insulating film, and a conductive pathis formed through the third insulating film and extended to the contactportion of the conductor.

[0030] In another aspect of the present invention, in a manufacturingprocess of a semiconductor device, further a conductor having a contactportion to which another silicon nitride film is applied is embedded inthe third insulating film, and a conductive path is formed through thethird insulating film and another silicon nitride film and is extendedto the contact portion of the conductor.

[0031] In another aspect of the present invention, in a manufacturingprocess of a semiconductor device, an insulating film is applied to aprincipal plane of a semiconductor substrate having a plurality ofcontact portions. A conductive section having a contact portion isformed on the insulating film. The conductive section is covered with asilicon nitride film. The silicon nitride film and the insulating filmis covered with another insulating film. A conductive path is formedthrough the insulating film and the silicon nitride film and extended tothe contact portion of the conductive section.

[0032] Further, in another aspect of the present invention, in amanufacturing process of a semiconductor device, a conductive path isformed through the insulating film and another insulating film, and isextended to the contact portion of the semiconductor substrate.

[0033] Other features and advantages of the invention will be apparentfrom the following description.

BRIEF DESCRIPTION OF DRAWINGS

[0034]FIG. 1(a) is a plan view and FIG. 1(b) is a cross sectional viewfor explaining a structure of a semiconductor device in accordance withthe first embodiment of the present invention;

[0035]FIG. 2 through FIG. 5 are views for explaining a manufacturingmethod of a semiconductor device in accordance with the secondembodiment of the invention;

[0036]FIG. 6(a) is a plan view and FIG. 6(b) is a cross sectional viewfor explaining a structure of a semiconductor device in accordance withthe third embodiment of the invention;

[0037]FIG. 7 through FIG. 10 are views for explaining a manufacturingmethod of a semiconductor device in accordance with the fourthembodiment of the invention;

[0038]FIG. 11 is a cross sectional view for explaining a structure of asemiconductor device in accordance with the fifth embodiment of theinvention;

[0039]FIG. 12 through FIG. 14 are views for explaining a manufacturingmethod of a semiconductor device in accordance with the sixth embodimentof the invention;

[0040]FIG. 15 is a cross sectional view for explaining the structure ofthe semiconductor device in accordance with the seventh embodiment ofthe invention;

[0041]FIG. 16 through FIG. 18 are views for explaining the manufacturingmethod of the semiconductor device in accordance with the eighthembodiment of the invention;

[0042]FIG. 19 is a cross sectional view for explaining a structure ofthe semiconductor device in accordance with the ninth embodiment of theinvention;

[0043]FIG. 20 through FIG. 24 are views for explaining the manufacturingmethod of the semiconductor device in accordance with the tenthembodiment of the invention;

[0044]FIG. 25 is a cross sectional view for explaining a structure of asemiconductor device in accordance with the eleventh embodiment of theinvention;

[0045]FIG. 26 through FIG. 28 are views for explaining a manufacturingmethod of a semiconductor device in accordance with the twelfthembodiment of the invention;

[0046]FIG. 29 is a view showing a conventional DRAM structure.

[0047]FIG. 30 is a view for explaining a self-alignment contacttechnology using silicon nitride film.

[0048]FIG. 31 is a view showing a state of conductive path (i.e.aluminum contact) provided through the interlayer insulating film.

BEST MODE FOR CARRYING OUT THE INVENTION

[0049] First Embodiment

[0050] FIGS. 1(a) and 1(b) illustrate a structure of a semiconductordevice according to the first embodiment of the present invention, andwhich FIG. 1(a) shows a plan view of the structure, and FIG. 1(b) showsa sectional view of the structure. In the explanation of thisembodiment, a DRAM is described as an example of the semiconductordevice. The illustrated semiconductor device (DRAM) is comprised of amemory cell array section A without aluminum contact, and peripheralcircuit section B having a substrate, a transfer gate, bit lines, and analuminum contact with a cell plate.

[0051] As shown in the drawings, the semiconductor device comprises asemiconductor substrate 1, an oxide film 2 serving as a first insulatingfilm, and oxide film 3 serving as a second insulating film, a siliconnitride film 4, an interlayer insulating film or interlayer oxide film 5serving as a third insulating film, conductive sections 6 and 7 on thefirst oxide film 2, conductive sections 8 and 9 in the interlayerinsulating film 5, another conductive section 10 in the interlayerinsulating film 5, and its contact passage 11.

[0052] The semiconductor substrate 1 has a number of elements formed ona principal plan thereof. On the semiconductor substrate 1, a contactportion 1 a for contacting between layers and a contact portion 1 b forcontacting the conductive section 10 are shown. The first oxide film 2is applied to the principal plane of the semiconductor substrate 1 toform a gate oxide film, and an opening 2 a is provided in the contactportion 1 a of the semiconductor substrate 1. The second oxide film 3 isapplied to the conductive sections 6 and 7, and is formed to cover them.The second oxide film 3 covering the conductive section 6 has an opening3 a provided in the contact portion 6 a of the conductive section 6.

[0053] The silicon nitride film (Sin) 4 is applied to the first oxidefilm 2 and second oxide film 3, and an opening 4 a is provided in thecontact portion 1 a of the principal plane of the semiconductorsubstrate 1, and an opening 4 b is provided in the contact portion 6 aof the conductive section 6. The silicon nitride film 4 is formed forthe purpose of self-alignment contact in the memory cell array sectionA, and is formed simultaneously also in the peripheral section B.

[0054] The interlayer insulating film 5 is applied to a region aroundthe contact portion 1 a of the principal plane of he semiconductorsubstrate 1, to the first oxide film 2 and second oxide film 3 aroundthe contact portion 6 a of the conductive section 6, and to the siliconnitride film 4, and the interlayer insulating film 5 has an opening 5 aprovided in the contact portion 1 a of the semiconductor substrate 1 andanother opening 5 b provided in the contact portion 6 a of theconductive section 6. The interlayer insulating film 5 has a furtheropening 5 c provided in a contact portion 8 a of the conductive section8 disposed at a middle position in the interlayer insulating film 5, anda further opening 5 d provided in a contact portion 9 a of theconductive section 9.

[0055] The conductive section 6 is disposed so as to project from thefirst oxide film 2, and is a conductive part to be a word line servingas a transfer gate. The conductive section 7 is disposed so as toproject from the electrode or word line. The conductive section 8 is aconductive part serving as a bit line disposed at a middle position inthe interlayer insulating film 5, and has a contact portion 8 a. Theconductive section 9 is a conductive part serving as a cell pate of acapacitor disposed at a middle position in the interlayer insulatingfilm 5, and it has a contact portion 9 a. The conductive section 10 is aconductive part serving as bit line disposed at a middle position in theinterlayer insulating film 5 in the same manner as the conductivesection 8, and has contact passage 11.

[0056] In the memory cell array section A of this semiconductor device,there are bit line contact passage 11 and storage node contact (notshown) serving as conductive paths to the semiconductor substrate 1, anda self-alignment technology is utilized herein.

[0057] On the other hand, in the peripheral circuit section B, there isa bit line contact passage 11 which is formed simultaneously with thebit line contact passage 11 of the memory cell array section A. Further,there are upper metal leads, so-called aluminum contacts, in theopenings 5 a, 5 b, 5 c, 5 d of the interlayer insulating film 5, formedto serve as interlayer conductive paths, extending to the contactportion 1 a of the semiconductor substrate 1, contact portion 6 a of theconductive section 6, contact portion 8 a of the conductive section 8 inthe middle position, and contact portion 9 a of the conductive section 9in the middle position, respectively.

[0058] As described above, in the semiconductor device according to thisfirst embodiment, the silicon nitride film is removed from thesurrounding area of the contact portions to which contact with the uppermetal lead (aluminum contact) is made. As a result, there is no nitridefilm used for self-alignment at all portions of aluminum contacts, andhe etching stop on the nitride film is not caused.

[0059] This first embodiment may be also understood as follows. That is,in the semiconductor device according to the first embodiment, andinsulating film including the insulating films 2, 3, and 5 is applied tothe principal plane of the semiconductor substrate 1, and in thissemiconductor film, the conductive section 6 is disposed near theprincipal plane of the semiconductor substrate 1. Further, the siliconnitride film 4 is disposed in this insulating film so as to cover theprincipal plane of the semiconductor substrate 1 and the conductivesection 6. Furthermore, a conductive path is provided through theinsulating film and silicon nitride film 4 extending to the contactportion 6 a of the conductive section 6. Similarly, a conductive path isprovided through the insulating film and silicon nitride film 4extending to the contact portion 1 a of the semiconductor substrate 1.The opening diameter of the silicon nitride film 4 is formed to belarger than those of the conductive paths. In the insulating film, otherconductive section 8 and 9 are disposed, and conductive paths areprovided through the insulating film extending to the contact portions 8a and 9 a of those conductive sections.

[0060] Second embodiment

[0061] FIGS. 2 to 5 are to explain a manufacturing process of asemiconductor device according to the second embodiment of theinvention, and this manufacturing process is suitable for manufacturingthe semiconductor device of the structure as described in the firstembodiment. In the drawings, the same reference numerals as in FIG. 1designate same or like parts.

[0062] Now the manufacturing process will be described. First, as shownin FIG. 2, a first insulating film (oxide film) 2 is applied to theprincipal plane of the semiconductor substrate 1. On a part of thisfirst oxide film 2, a conductive section (transfer gate) 6 and aconductive section (word line) 7 are formed so as to project therefrom.These conductive sections 6 and 7 are further covered with a secondinsulating film (oxide film) 3.

[0063] Further, a silicon nitride film 4 is applied to the entiresurface. This silicon nitride film 4 is formed for self-alignmentcontact in the memory cell array section A, and is simultaneously formedalso in the peripheral section B. Furthermore, a fourth insulating film(silicon oxide film) 5′ is applied to the entire surface. Thereafter, aresist 12 is applied to the entire surface, and openings are provided ina region around the contact portion 1 a of the semiconductor substrate 1and in a region around the contact portion 6 a of the conductive section6.

[0064] Then, as shown in FIG. 3, the fourth oxide film 5′ is selectivelyremoved from this opening by etching. Further, as shown in FIG. 4, theresist 12 is removed. And employing the remaining fourth oxide film 5′as a mask, a wet etching is performed with the use of hot phosphoricacid or the like, whereby the silicon nitride film 4 is selectivelyremoved.

[0065] Then, as shown in FIG. 5, the silicon oxide film 5 serving as theinterlayer insulation layer is applied and is flattened on the entiresurface including the upper parts of the first and second oxide films 2and 3 on the semiconductor substrate 1. The remaining fourth oxide film5′ is integrated with the interlayer oxide film 5 and, therefore, is notshown separately in the drawing. In this process, an opening is providedthrough the silicon nitride film 4 on the bit line contact portion 1 bin the principal plane of the semiconductor substrate 1 and the firstoxide film 2, and a bit line contact passage 11 is formed therein.Further, the conductive section (bit line) 8 and conductive section (bitline) 10 are disposed at the middle position of the intelayer oxide film5. Furthermore, a conductive section (cell plate) 9 is likewise formed,and is buried i the interlayer oxide film 5.

[0066] Thereafter, by applying a resist 13 and by making openings atlocations for aluminum contacts from above, the interlayer oxide film 5is selectively etched, whereby openings are provided to prepareconductive paths to the contact portion 1 a of the semiconductorsubstrate 1, contact portion 6 a of the conductive section 9. Then, theresist 13 is removed, and utilizing the mentioned openings of theinterlayer oxide film 5, the aluminum contacts are accomplished to serveas conductive paths to the circuit on the upper side of the interlayerinsulating film 5.

[0067] Thus, in the first embodiment, the oxide film 5′ is overlaid onthe nitride film 4, and the oxide film 5′ is patterned by the resist 12.And after removing the resist 12, the wet etching is performed with theuse of hot phosphoric acid or the like employing the oxide film 5′ as amask.

[0068] As described above, according to the manufacturing method of thesemiconductor device in this embodiment, the surrounding silicon nitridefilm is removed from the contact portions to be put in contact with themetal lead (aluminum contact). As a result, the nitride film used inself-alignment is removed from all aluminum contact area, and theproblem of etching stop on the nitride film is overcome. In theconventional method of cutting off the nitride film by dry etching usingthe resist as a mask, there has been a possibility that the selectionratio with respect to the oxide film is not enough, whereby, thesubstrate 1 might be cut off. On the other hand, in this embodiment, byusing a wet etching of which selection ratio with respect to the oxidefilm is large enough, a stable manufacturing process free from erroneouscutting of substrate or free from plasma damage is achieved.

[0069] This embodiment my be also stated as follows. That is, in themanufacturing process according to this embodiment, the first insulatingfilm 2 is applied on the principal plane of the semiconductor substrate1. The conductive section 6 is formed on the first insulating film 2,and then the conductive section 6 is covered with the second insulatingfilm 3. The first insulating film 2 and second insulating film 3 arecovered with the silicon nitride film 4. The silicon nitride film 4 isremoved at least in the region of the contact portion 6 a of theconductive section and the removed part is covered with the thirdinsulating film 5. A plurality of openings are provided in the thirdinsulating film 5, and conductive paths are provided through the thirdinsulating film 5 extending to the contact portion 6 a of the conductivesection 6.

[0070] Third embodiment

[0071] FIGS. 6(a) and (b) illustrate the structure of a semiconductordevice according to the third embodiment of the invention, and in whichFIG. 6(a) is a plan view, and FIG. 6(b) is a sectional view of thestructure. The illustrated semiconductor device (DRAM) is comprised of amemory cell array section A without aluminum contact, and a peripheralcircuit section B having a substrate, transfer gate, bit line, andaluminum contact on cell plate. In the drawings, same reference numeralsas in FIG. 1 designate same or equivalent parts respectively.

[0072] As shown in the drawings, the semiconductor device comprises asemiconductor substrate 1, a first oxide film 2, a second oxide film 3,a silicon nitride film 4, an interlayer insulating film 5, a conductivesection 6 and a conductive section 7 formed on the first oxide film 2, asecond oxide film 3, a silicon nitride film 4, an interlayer insulatingfilm 5, a conductive section 6 and a conductive section 7 formed on thefirst oxide film 2, a conductive section 8 and a conductive section 9disposed at the middle position in the interlayer insulating film 5, afurther conductive section 10 disposed at the middle position in theinterlayer insulating film 5, and a contact a passage 11 thereof.

[0073] The semiconductor substrate 1 may have a number of elementsformed on a principal plane thereof. A contact portion 1 a forcontacting the conductive section 10 are shown herein. The first oxidefilm 2 is applied to the principal plane of the semiconductor substrate1 to be a gate oxide film, and an opening 2 a is provided in the contactportion 1 a of the semiconductor substrate 1.

[0074] The second oxide film 3 is applied to cover the conductivesections 6 and 7 disposed on the first oxide film 2. The second oxidefilm 3 covering the conductive section 6 has an opening 3 a provided inthe contact portion 6 a of the conductive section 6.

[0075] The silicon nitride film (SiN) 4 is applied to the first oxidefilm 2 and second oxide film 3 in the memory cell array section A. Inthe peripheral circuit section B having aluminum contact, the siliconnitride film (SiN) 4 is applied to the oxide film 2 only in the regionsurrounding the line contact portion 1 b and around the bit line contactpassage 11. This silicon nitride film 4 is formed for the purpose ofself-alignment contact in the memory cell array section A, and issimultaneously formed also in the peripheral section B.

[0076] The interlayer insulating film 5 is applied to the first oxidefilm 2, second oxide film 3 and silicon nitride film 4, and has anopening 5 a provided in the contact portion 1 a of the semiconductorsubstrate 1 and another opening 5 b provided in the contact portion 6 aof the conductive section 6. Further, an opening 5 c is provided in acontact portion 8 a of the conductive section 8 at the middle positionburied in the interlayer insulating film 5, and an opening 5 d isprovided in a contact portion 9 a of the conductive section 9 in themiddle position.

[0077] The conductive section 6 is a conductive part to be a word lineserving as a transfer gate. The conductive section 7 is a conductivepart to be a gate electrode or word line. The conductive suction 8 is aconductive part serving as a bit line disposed at a middle positionburied in the interlayer insulating film 5 and has a contact portion 8a. The conductive section 9 is a conductive part serving as a cell plateof capacitor buried in the interlayer insulating film 5 and has acontact portion 9 a. The conductive section 10 is a conductive partserving as a bit line in the same manner as the conductive section 6 atthe middle position buried in the interlayer insulating film 5 and has acontact passage 11 to the semiconductor substrate 1.

[0078] In the memory cell array section A of this semiconductor device,there is a bit line contact passage 11 and storage node contact (notshown) serving as conductive paths to the semiconductor substrate 1, andherein a self-alignment technology is utilized.

[0079] On the other hand, in the peripheral circuit section B, there isshown a bit line contact passage 11 which is formed simultaneously withthe bit line contact passage 11 of the memory cell array section A.Further, there are upper metal leads, so-called aluminum contacts, inthe opening 5 a, 5 b, 5 c, 5 d of the interlayer insulating film 5,formed to serve as interlayer conductive paths, extending to the contactportion 1 a of the semiconductor substrate 1, contact portion 6 a of theconductive section 6, contact portion 8 a of the conductive section 8 inthe middle position, and contact portion 9 a of the conductive section 9in the middle position, respectively.

[0080] There are also bit line 10 and a contact passage 11 thereofformed simultaneously with the bit line 10 and its contact portion 11 inthe memory cell array section A.

[0081] In the semiconductor device according to this embodiment, thenitride film 4 is left only around the bit line contact 1 b is leftbecause the silicon nitride film is necessary in the self-alignmenttechnology in the same way as in the bit line contact of the memory cellarray section.

[0082] As a result of adopting the above construction, the nitride film4 employed in the self-alignment technique is removed from all aluminumcontact area in the peripheral circuit section B, so that the problem ofetching stop on the nitride film 4 is overcome. In this embodiment,furthermore, the area where the silicon nitride film is left in theperipheral circuit section is minimized except in the memory cell arraysection. As a result of minimizing the silicon nitride film of highdielectric constant disposed among the leads in the peripheral circuitsection, there is an advantage such that the capacity among the leadsmay be reduced, and the electric characteristics, particularly operatingspeed, may be improved.

[0083] This embodiment may be also restated as follows. That is, in thesemiconductor device of the embodiment, an insulating film including theinsulating films 2, 3, 5 is applied to the semiconductor substrate 1having contact portions 1 a and 1 b on its principal plane, and in thisinsulating film and is left so as to cover the surrounding area of thecontact portion 1 b of the principal plane of the semiconductorsubstrate 1, and is removed in the region of the contact portion 1 a andconductive section 6. Furthermore, another conductive section 10 isdisposed in the insulating film, and a contact passage 11 is formedextending from this conductive section 10 to the contact portion 1 b ofthe semiconductor substrate 1 through the insulating film and siliconnitride film 4. In addition, a conductive path extending to the contactportion 1 a of the semiconductor substrate 1 are formed through theinsulating film. Moreover, conductive paths extending to the contactportions 8 a and 9 a of the conductive sections 8 and 9 in theinsulating film are respectively provided through the insulating film.

[0084] Fourth embodiment

[0085] FIGS. 7 to 10 illustrate the manufacturing method of asemiconductor device according to the fourth embodiment of theinvention, and this manufacturing process is suitable for manufacturingthe semiconductor device of the structure as described in the thirdembodiment. In the drawings, same reference numerals as in FIG. 1 orFIG. 2 designate same or like parts.

[0086] Now the manufacturing process is described. As shown in FIG. 7, afirst insulating film (oxide film) 2 is applied to the principal planeof the semiconductor substrate 1. On a part of this first oxide film 2,a conductive section (transfer gate) 6 and a conductive section (wordline) 7 are formed. These conductive sections 6 and 7 are furthercovered with a second insulating film (oxide film) 3. Further, a siliconnitride film 4 is applied to the entire surface. This silicon nitridefilm 4 is applied to the entire surface. This silicon nitride film 4 isformed for self-alignment contact in the memory cell array section A,and is simultaneously formed also in the peripheral section B. Further,a fourth insulating film (silicon oxide film) 5′ is applied to theentire surface. In the peripheral circuit section B having aluminumcontacts, the resist 12 is removed while being left only in the regionaround the contact portion 1 b of the principal plane of thesemiconductor substrate 1 which is to come in contact with the bit line.Then, as shown in FIG. 8, the fourth oxide film 5′ is selective removeby etching from the region where the resist 12 is removed.

[0087] Then, as shown in FIG. 9, the remaining resist 12 is removed, andutilizing the selectively etched fourth oxide film 5′ as a mask, a wetetching is performed by hot phosphoric acid or the like, and the siliconnitride film 4 is left only around the bit line contact 1 b. In theremaining regions, the silicon nitride film 4 is selectively removed byetching.

[0088] Then, as shown in FIG. 10, the silicon oxide film 5 serving asthe interlayer insulation layer is applied and flattened on the entiresurface including the firs and second oxide films 2 and 3 and thesilicon nitride film 4 on the semiconductor substrate 1. The remainingfourth on the semiconductor substrate 1. The remaining fourth oxide film5′ is integrated with the interlayer oxide film 5 and, therefore, is notshown separately in the drawing. In this process, an opening is providedthrough the silicon nitride film 4 and the first oxide film 2 on the bitline contact portion 1 b in the principal plane of the semiconductorsubstrate 1, and a bit line contact passage 11 is disposed therein.Further, the conductive section (bit line) 8 and conductive section (bitline) 10 are disposed in the middle position of the interlayer oxidefilm 5. Furthermore, a conductive section (cell plate) 9 is likewiseformed, and buried into the interlayer oxide film 5.

[0089] Thereafter, by applying a resist 13 to the entire surface and bymaking opening at locations where an aluminum contact is to be made fromabove, the interlayer oxide film 5 is selectively etched, wherebyopening are provided for conductive paths to the contact portion 1 a ofthe semiconductor substrate 1, contact portion 6 a of the conductivesection 6, contact portion 8 a of the conductive section 8, and contactportion 9 a of the conductive section 9. Then, the resist 13 is removed,and utilizing the openings of the interlayer oxide film 5, the aluminumcontacts are accomplished to serve as conductive paths to the upperpart.

[0090] Thus, in this embodiment, the oxide film 5′ is overlaid on thenitride film 4, and the oxide film 5′ is patterned by the resist 12, andafter removing the resist 12, the wet etching is performed with the useof hot phosphoric acid or the like employing the oxide film 5′ as amask.

[0091] As described above, in the manufacturing process of thesemiconductor device according to this embodiment, the nitride film 4used in self-alignment is removed from all area for aluminum contacts inthe peripheral circuit section B, and the problem of etching stop on thenitride film 4 is overcome. Further, in this embodiment, area of thesilicon nitride 4 left in the peripheral circuit section B is minimizedother than the memory cell array section A. Therefore, as a result ofminimizing the silicon nitride film of high dielectric constant disposedamong the leads in the peripheral circuit section B, the capacity amongthe leads may be reduced, and the electric characteristics, particularlyoperating speed, may be improved.

[0092] In the conventional method of cutting off the nitride film by dryetching using the resist as a mask, there has been a possibility thatthe selection ration with respect to the oxide film is not enough,whereby the substrate 1 might be cut off. On the other hand, in thisembodiment, by using a wet etching of which selection ratio with respectto the oxide film is large enough, a stable manufacturing process isachieved free from erroneous cutting of substrate or free from plasmadamage.

[0093] This embodiment may be also stated as follows. That is, in themanufacturing process according to this embodiment, the first insulatingfilm 2 is applied on the principal plane of the semiconductor substrate1, and the conductive section 6 is formed on this first insulating film2. The conductive section 6 is covered with the second insulating film3, and then the first insulating film 2 and second insulating film 3 arecovered with the silicon nitride film 4. Next, the silicon nitride film4 is removed while leaving it only at a part of the principal plane,i.e. the region for making bit line contact, of the semiconductorsubstrate 1. Then the whole surface is covered with the third insulatingfilm 5, and a plurality of openings are providing in the thirdinsulating film 5. Further, a conductive path is provided through thethird insulating film 5 extending to the contact portion 6 a of theconductive section 6.

[0094] To be summarized, an essential point of the first through fourthembodiments is a construction in which an etching stop material foroxide film such as nitride film is place on a lower lead (transfergate), and the etching stop material is removed in the peripheralcircuit section for making aluminum contacts other than the memory cellarray section. In the first and second embodiments, the silicon nitridefilm SiN is removed only around desired contacts in the peripheralcircuit section which needs aluminum contracts, whereas in the third andfourth embodiments, the silicon nitride film SiN is left only around thebit line contact in the peripheral circuit section which needs aluminumcontacts.

[0095] Fifth embodiment

[0096]FIG. 11 illustrates a sectional view of the structure of asemiconductor device according to the fifth embodiment of the invention.The illustrated semiconductor device (DRAM) is comprised of a memorycell array section A without aluminum contact, and peripheral circuitsection B having a substrate, transfer gate, bit line, and aluminumcontacts on a cell plate. In the drawing, same reference numerals as inFIG. 1 designate same or like parts respectively.

[0097] As shown in the drawing, the semiconductor device comprises asemiconductor substrate 1, a first insulating film (oxide film) 2, asecond insulating film (oxide film) 3, a silicon nitride film 4, a thirdinsulating film (interlayer insulating film) 5, a conductive section(transfer gate) 6 and a conductive section (word line) 7 on the firstoxide film 2, a conductive section (bit line) 8 and a conductive section(cell plate) 9 buried at the middle position in the interlayerinsulating film 5, a further conductive section (bit line) 10 buried atthe middle position in the interlayer insulating film 5, and a contactpassage 11 thereof.

[0098] The semiconductor substrate 1 has a number of elements formed ona principal plane thereof, and a contact portion 1 a for contactingbetween the layers and a contact portion 1 b for contacting theconductive section (bit line) 10 are shown herein. The first oxide film2 is applied to the principal plane of the semiconductor substrate 1,and an opening 2 a is provided in the contact portion 1 a of thesemiconductor substrate 1.

[0099] The second oxide film 3 is applied to cover the conductivesections 6 and 7 disposed on the first oxide film 2. The second oxidefilm 3 covering the conductive section 6 has an opening 3 a provided inthe contact portion 6 a of the conductive section 6.

[0100] The silicon nitride film (SiN) 4 is applied to the first oxidefilm 2 and second oxide film 3, and has an opening 4 a provided in thecontact portion 1 a of the principal plan of he semiconductor substrate1 and an opening 4 b provided in the contact portion 6 a of theconductive section 6. This silicon nitride film 4 is formed for thepurpose of self-alignment contact in the memory cell array section A andis simultaneously formed also in the peripheral circuit section B.

[0101] The interlayer insulting film 5 is applied to the silicon nitride4, and has an opening 5 a provided in the contact portion 1 a of thesemiconductor substrate 1 and an opening 5 b provided in the contactportion 6 a of the conductive section 6. Further, an opening 5 c isprovided in a contact portion 8 a of the conductive section 8 at themiddle position buried in the interlayer insulating film 5, and anopening 5 d is provided in a contact portion 9 a of the conductivesection 9.

[0102] The conductive section 6 is formed on a part of the first oxidefilm 2 to project from the first oxide film 2, and is a conductive partto be a word line serving as a transfer gate. The conductive section 7is formed on a part of the first oxide film to project from the firstoxide film 2, and is a conductive part to be a gate electrode or wordline. The conductive section 8 is a conductive part serving as a bitline formed at a middle position in the interlayer insulating film 5with a certain distance from the principal plane of he semiconductorsubstrate 1, and has a contact portion 8 a. The conductive section 9 isa conductive part serving as a cell plate of a capacitor formed at themiddle position in the interlayer insulating film 5 with a certaindistance from the principal plane of the semiconductor substrate 1, andhas a contact portion 9 a. The conductive section 10 is a conductivepart serving as a bit line formed, in the same manner as the conductivesection 8, at another middle position buried in the interlayerinsulating film 5, and has a contact passage 11.

[0103] In the memory cell array section A of this semiconductor device,there are bit line contact passage 11 serving as conductive path to thesemiconductor substrate 1 and storage node contact (not shown), andherein a self-alignment technology is utilized.

[0104] On the other hand, in the peripheral circuit section B, there isa bit line contact passage 11 which is formed simultaneously with thebit line contact passage 11 of the memory cell array section A.Furthermore, in the openings 5 a, 5 b, 5 c, 5 d, of the interlayerinsulating film 5, there are upper metal leads, so-called aluminumcontacts, formed to serve as interlayer conductive paths, extending tothe contact portion 1 a of the semiconductor substrate 1, contactportion 6 a of the conductive section 6, contact portion 8 a of theconductive section 8 in the middle position, and contact portion 9 a ofthe conductive section 9 in the middle position, respectively.

[0105] In this embodiment, in the semiconductor device manufactured by ablanket SiN type self-alignment method, the aluminum contacts aresecurely made to the contact portion of the semiconductor substrate andto the contact portion of the transfer gate through the silicon nitridefilm.

[0106] This embodiment may be also restated as follows. That is, in thesemiconductor device according to this embodiment, an insulating filmincluding the insulating films 2, 3, 5 is applied to the principal planeof the semiconductor substrate 1. Further, the silicon nitride film 4 isdisposed in this insulating film so as to cover the principal plane ofthe semiconductor substrate 1 and the conductive section 6. Furthermore,a conductive path is provided through the insulating film and thesilicon nitride film 4 extending to the contact portion 6 a of thementioned conductive section 6. Similarly, a conductive path is providedthrough the insulating film and silicon nitride film 4 extending to thecontact portion 1 a of the semiconductor substrate 1. The openingdiameter of the silicon nitride film 4 is the same as the diameter ofthese conductive paths, and they are closely adjacent each other. In theinsulating film, other conductive sections 8 and 9 are disposed, andconductive paths are respectively provided through the insulating filmextending to the contact portions 8 a and 9 a of those conductivesections 8 and 9.

[0107] Sixth embodiment

[0108] FIGS. 12 to 14 show a manufacturing process of a semiconductordevice according to the sixth embodiment of the invention, and thismanufacturing process is suitable for manufacturing the semiconductordevice of the structure as described in the fifth embodiment. In thedrawings, the same reference numerals as in FIG. 1 or FIG. 2 designatesame or like parts.

[0109] Now the manufacturing process is described. As shown in FIG. 12,a first insulating film (oxide film) 2 is applied to the principal planeof the semiconductor substrate 1. On a part of this first oxide film 2,a conductive section (transfer gate) 6 and conductive section (wordline) 7 are formed so as to project from the first oxide film 2. Theseconductive sections 6 and 7 are further covered with a second insultingfilm (oxide film) 3. Further, a silicon nitride film 4 is applied to theentire surface of the first oxide film 2 and second oxide film 3. Thissilicon nitride film 4 is formed self-alignment contact in the memorycell array section A, and is simultaneously formed also in theperipheral section B.

[0110] A third insulating film (silicon oxide film as interlayerinsulating film) 5 is applied and flattened on the silicon nitride film4. In this process, an opening is provided through the silicon nitridefilm 4 and the first oxide film 2 on the bit line contact portion 1 b inthe principal plane of the semiconductor substrate 1, and a bit linecontact passage 11 is disposed therein. Further, he conductive section(bit line) 8 and conductive section (bit line) 10 are disposed at themiddle positions with certain distances from the silicon nitride 4 onthe principal plane of the semiconductor substrate 1, and a contactpassage 11 extending to the semiconductor substrate 1 is formed from theconductive section 10. Furthermore, a conductive section (cell plate) 9is likewise formed, and buried into the interlayer oxide film 5.

[0111] Thereafter, a resist 13 is applied, and openings are provided atthe location of bit line 8 and cell plate 9 not covered with the siliconnitride film 4. The interlayer oxide film 5 is etched selectively, andthereby openings 5 c, 5 d extending to the contact portions 8 a, 9 a areformed.

[0112] Then, as shown in FIG. 13, the openings extending to the contactportions 8 a and 9 a of the bit line 8 and cell plate 9 are filled orcovered with resist, and openings in the resist 13 are formed at thelocations of the contact portion 1 a of the semiconductor substrate 1and the contact portion 6 a of the transfer gate 6 covered with thesilicon nitride film 4. Then, the interlayer oxide film 5 is etchedselectively, and thereby openings extending to the silicon nitride film4 are formed.

[0113] Subsequently, as shown in FIG. 14, from the opening 5 a at thelocation of the contact portion 1 a of the semiconductor substrate 1 andfrom the opening 5 b at the location of the contact portion 6 a of thetransfer gate 6, the silicon nitride film 4 and silicon oxide film 2 areetched, and thereby openings 5 a, 5 b extending to the contact portion 1a and contact portion 6 a are formed. Thereafter, the resist 13 isremoved, and aluminum contacts are made to serve as conductive paths tothe upper parts through these openings in the interlayer oxide film 5.

[0114] This embodiment shows a manufacturing process by a blanket SiNtype self-alignment method in which openings for aluminum contacts areprovided by etching in two steps using two masks. This process comprisesa first opening step for the contacts on the bit line 8 and on the cellplate 9 not having a nitride film in the opened holes, and a secondopening step for the contacts on the substrate 1 and transfer gate 6having a nitride film in the opened holes. In the first step, an openingis performed just by oxide film dry etching, and in the second step, theoxide film dry etching is followed by a nitride film etching and baselayer oxide film etching.

[0115] In this manner, the steps for opening the contact through anitride film are performed by separate etching. Therefore it is possibleto apply different etching specifications, whereby film thicknessreduction or penetration of upper lead due to over-etching may beeffectively prevented.

[0116] This embodiment may be also restated as follows. That is, in themanufacturing process according to this embodiment, the first insulatingfilm 2 is applied on the principal plane of the semiconductor substrate1, and the conductive section 6 is formed on the first insulating film2. Then the conductive section 6 is covered with the second insulatingfilm 3, and the first insulating film 2 and second insulating film 3 arecovered with the silicon nitride film 4. The third insulating film 5 isapplied to the silicon nitride film 4 surrounding another conductivesection 8. An opening through the third insulating film 5 is provided toform a conductive path extending through the third insulating film 5 tothe contact portion 8 a of the another conductive section 8 openings areprovided through the third insulating film 5 and silicon nitride film 4to form a conductive path extending to the contact portion 6 a of theconductive section 6 and a conductive path extending to the contactportion 1 a of the semiconductor substrate 1 respectively.

[0117] Seventh embodiment

[0118]FIG. 15 shows a sectional view of the structure of a semiconductordevice according to the seventh embodiment of the invention. Theillustrated semiconductor device (DRAM) is comprised of a memory cellarray section A having no aluminum contact, and a peripheral circuitsection B having a substrate, transfer gate, bit line, and aluminumcontacts on a cell plate. In the drawing, same reference numerals as inFIG. 1 designate the same or like parts respectively.

[0119] As shown in the drawing, the semiconductor device comprises asemiconductor substrate 1, a first insulating film (oxide film) 2, asecond insulating film (oxide film) 3, a silicon nitride film 4, a thirdinsulating (interlayer insulating film) 5, a conductive section(transfer gate) 6 and a conductive section (word line) 7 on the firstoxide film 2, a conductive section (bit line) 8 and a conductive section(cell plate) 9 buried at the middle position in the interlayerinsulating film 5, and a contact passage 11 thereof.

[0120] The semiconductor substrate 1 has a number of elements formed ona principal plane thereof, and a contact portion 1 a for contactingbetween the layers and a contact portion 1 b for contacting theconductive section 10 are shown herein. The first oxide film 2 isapplied to the principal plane of the semiconductor substrate 1, and anopening 2 a is provided in the contact portion 1 a of the semiconductorsubstrate 1.

[0121] The second oxide film 3 is applied to cover the conductivesections 6 and 7 disposed on the first oxide film 2. The second oxidefilm 3 covering the conductive section 6 has an opening 3 a provided inthe contact portion 6 a of the conductive section 6.

[0122] The silicon nitride film (SiN) 4 is applied to the first oxidefilm 2 and second oxide film 3, and has an opening 4 a provided in thecontact portion 1 a of the principal plan of the semiconductor substrate1 and an opening 4 b provided in the contact portion 6 a of theconductive section 6. This silicon nitride film 4 is formed for thepurpose of self-alignment contact in the memory cell array section A andis simultaneously formed also in the peripheral section B.

[0123] The interlayer insulating film 5 is applied to the siliconnitride film 4, and has an opening Sa provided in the contact portion 1a of the semiconductor substrate 1 and an opening 5 b provided in thecontact portion 6 a of the conductive section 6. Further, an opening 5 cis provided in a contact portion 8 a of the conductive section 8 at themiddle position buried in the interlayer insulating film 5, and anopening 5 d is provided in a contact portion 9 a of the conductivesection 9.

[0124] The conductive section 6 is formed on a part of the first oxidefilm 2 to project from the first oxide film 2, and is a conductive partto be a word line serving as a transfer gate. The conductive section 7is formed on a part of the first oxide film to project from the firstoxide film 2, and is a conductive part to be a gate electrode or wordline. The conductive section 8 is a conductive part serving as a bitline formed at a middle position in the interlayer insulating film 5with a certain distance from the principal plane of the semiconductorsubstrate 1, and has a contact portion 8 a. A silicon nitride film 4′ isapplied to the upper surface of the conductive section 8, and an openingis provided at the location of the contact portion 8 a of the conductivesection 8.

[0125] The conductive section 9 is a conductive part serving as a cellplate of the capacitor formed at the middle position in the interlayerinsulating film 5 with a certain distance from the principal plane ofthe semiconductor substrate 1, and has a contact portion 9 a. A siliconnitride film 4′ is applied to the upper surface of the conductivesection 9, and an opening is provided at the location of the contactportion 9 a of the conductive section 9. The conductive section 10 is aconductive part serving as a bit line formed, in the same manner as theconducive section 8, at another middle position buried in the interlayerinsulating film 5, and has a contact passage 11.

[0126] In the memory cell array section A of this semiconductor device,there are bit line contact passages 11 serving as conductive paths tothe semiconductor substrate 1 and storage node contact (not shown), andherein a self-alignment technology is utilized.

[0127] On the other hand, in the peripheral circuit section B, a bitline contact passage 11 is formed simultaneously with the bit linecontact passage 11 of the memory cell array section A. Furthermore, inthe openings 5 a, 5 b, 5 c, 5 d of the interlayer insulating film 5, theupper metal leads, so-called aluminum contacts, are formed to serve asinterlayer conductive paths, extending to the contact portion 1 a of thesemiconductor substrate 1, contact portion 6 a of the conductive section6, contact portion 8 a of the conductive section 8 in the middleposition, and contact portion 9 a of the conductive section 9 in themiddle position, respectively.

[0128] In the structure according to this embodiment, the siliconnitride film is placed on all leads and substrate where aluminumcontacts are to be formed. The aluminum contact holes are once receivedby the nitride film, and after removing the nitride film by varying thegas and etching conditions, the contact holes are formed by applying aslight oxide film etching.

[0129] In this embodiment, the aluminum contacts may securely formed toserve as conductive paths to the upper layer in such a manner as tosecurely pass through the silicon nitride film 4 used in theself-alignment contact. Further, since every conductive section issimilarly covered with silicon nitride film, the conducive sections maybe processed and treated in like manner.

[0130] This embodiment may be also restated as follows. That is, in thesemiconductor device according to this embodiment, an insulating filmincluding the insulating films 2, 3, 5, is applied to the principal planof the semiconductor substrate 1, and in this semiconductor film, theconductive section 6 is disposed near the principal plan of thesemiconductor substrate 1. Further, the silicon nitride film 4 isdisposed in this insulating film so as to cover the principal plan ofthe semiconductor substrate 1 and the conductive section 6. Furthermore,a conductive path is provided through the insulating film and thesilicon nitride film 4 extending to the contact portion 6 a of theconductive 6. Similarly, a conductive path is provided through theinsulating film and silicon nitride film 4 extending to the contactportion 1 a of the semiconductor substrate 1. The opening diameter ofthe silicon nitride film 4 is the same as the diameter of theseconductive paths, and they are closely adjacent each other. In theinsulating film, other conductive sections 8 and 9 to which the siliconnitride film 4′ is applied are disposed, and conductive paths arerespectively provided through the insulating film and the siliconnitride film 4′ extending to the contact portions 8 a and 9 a of thoseconductive sections 8 and 9.

[0131] In the semiconductor devices according to the foregoing first,third, fifth and seventh embodiments, the silicon nitride film is formedfor the self-alignment contact in the blanket SiN method in the memorycell array section, and leads, i.e., so called aluminum contacts areprovided from the upper layer through the silicon nitride film formedsimultaneously in the peripheral circuit section. More specifically, inthe first and third embodiments among these embodiments, the size of theopening of the silicon nitride film is larger than that of theconductive paths with sufficient allowance, i.e., larger than the sizeof the diameter of the aluminum contact holes. On the other hand, in thefifth and seventh embodiments, the size of the opening of the siliconnitride film is same as that of the conductive paths, i.e., same as thesize of the diameter of the aluminum contact holes.

[0132] Eighth embodiment

[0133] FIGS. 16 to 18 illustrate a manufacturing process of asemiconductor device according to the eighth embodiment of theinvention, and this manufacturing process is suitable for manufacturingthe semiconductor device of the structure as described in the seventhembodiment. In the drawings, the same reference numerals as in FIG. 1 orFIG. 2 designate same or like parts.

[0134] Now the manufacturing process is described. As shown in FIG. 16,a first insulating film (oxide film) 2 is applied to the principal planeof the semiconductor substrate 1. On a part of this first oxide film 2,a conductive section (transfer gate) 6 and a conductive section (wordline) 7 are formed so as to project from the first oxide film 2. Theseconductive sections 6 and 7 are further covered with a second insulatingfilm (oxide film) 3. Further, a silicon nitride film 4 is applied to theentire surface of the first oxide film 2 and second oxide film 3. Thissilicon nitride film 4 is formed for self-alignment contact in thememory cell array section A, and is simultaneously formed also n theperipheral section B.

[0135] A third insulating film (silicon oxide film as an interlayerinsulating film) 5 is applied and flattened on the entire surface of thesilicon nitride film 4. In this process, an opening is provided throughthe silicon nitride film 4 and the first oxide film 2 on the bit linecontact portion 1 b in the principal plane of the semiconductorsubstrate 1, and a bit line contact passage 11 is disposed therein.Further, the conductive section (bit line) 8 and conductive section (bitline) 8 and conductive section (bit line) 10 are disposed at the middleposition with a certain distance from the silicon nitride film 4 on theprincipal plane of the semiconductor substrate 1. The silicon nitridefilm 4′ is applied to the upper surface of the bit lines 8 and 10.Furthermore, the conductive section (cell plate) 9 is disposed likewisein the interlayer oxide film 5 on which upper surface the siliconnitride films 4′ is applied.

[0136] Thereafter, as shown in FIG. 17, a resist 13 is applied to theentire surface of the interlayer oxide film 5, and openings are providedthrough this resist 13 at the positions corresponding to the contactportion 1 a of the semiconductor substrate 1, contact portion 6 a of theconductive section 6, contact portion 8 a of the bit line 8, and contactportion 9 a of the cell plate 9. Then the interlayer oxide film 5 isselectively etched from these openings, whereby openings 5 a, 5 b, 5 c,5 d are formed reaching to the silicon nitride films 4 or 4′.

[0137] Subsequently, as shown in FIG. 18, the silicon nitride film 4 isetched from these openings, thereby forming openings extendingrespectively to the contact portion 8 a of the bit line 8 and thecontact portion 9 a of the cell plate 9. In the openings in the contactportion 1 a of the semiconductor substrate 1 and the contact portion 6 aof the conductive section 6, the silicon nitride film 4 is removed, butthe oxide film 2 or 3 still remains. Therefore the remaining oxide filmis removed by subsequent oxide interlayer insulating film) 5 is appliedand flattened on the entire surface of the silicon nitride film 4. Inthis process, an opening is provided through the silicon nitride film 4and the first oxide film 2 on the bit line contact portion 1 b in theprincipal plane of the semiconductor substrate 1, and a bit line contactpassage 11 is disposed therein. Further, the conductive section (bitline) 8 and conductive section 9 bit line) 10 are disposed at the middleposition with a certain distance from the silicon nitride film 4 on theprincipal plane of the semiconductor substrate 1. The silicon nitridefilm 4′ is applied to the upper surface of the bit lines 8 and 10.Furthermore, the conductive section (cell plate) 9 is disposed likewisein the interlayer oxide film 5 on which upper surface the siliconnitride films 4′ is applied.

[0138] Thereafter, as shown in FIG. 17, a resist 13 is applied to theentire surface of the interlayer oxide film 5, and openings are providedthrough this resist 13 at the positions corresponding to the contactportion 1 a of the semiconductor substrate 1, contact portion 6 a of theconductive section 6, contact portion 8 a of the bit line 8, and contactportion 9 a of the cell plate 9. Then the interlayer oxide film 5 isselectively etched from these openings, whereby openings 5 a, 5 b, 5 c,5 d are formed reaching to the silicon nitride films 4 or 4′.

[0139] Subsequently, as shown in FIG. 18, the silicon nitride film 4 isetched from these openings, thereby forming openings extendingrespectively to the contact portion 8 a of the bit line 8 and thecontact portion 9 a of the cell plate 9. In the openings in the contactportion 1 a of the semiconductor substrate 1 and the contact portion 6 aof the conductive section 6, the silicon nitride film 4 is removed, butthe oxide film 2 or 3 still remains. Therefore the remaining oxide filmis removed by subsequent oxide film etching, thereby the openings 5 aand 5 b are formed reaching to the contact portion 1 a and contactportion 6 a, respectively. Thereafter, the resist 13 is removed, andaluminum contacts are made to serve as conductive paths to the upperparts through these openings in the interlayer oxide film 5.

[0140] In the manufacturing process according to this embodiment, thesilicon nitride film is place on all leads and substrate, where aluminumcontacts are to be formed. The aluminum contact holes are once receivedby the nitride film and after removing the nitride film by varying thegas and etching conditions, the contact holes are accomplished byapplying a slight oxide film etching.

[0141] In this manner, it is certain that shallow contacts receives arather longer etching time than required as compared with deep contactssuch as substrate contacts. Nevertheless, there is an advantage that theleads are not cut off because they are covered with a nitride filmserving as an etching stopper.

[0142] This embodiment may be also restated as follows. That is, in themanufacturing process according to this embodiment, the first insulatingfilm 2 is applied on the principal plane of the semiconductor substrate1, and the conductive section 6 is formed on this first insulating film2. Then the conductive section 6 is covered with the second insulatingfilm 3, and further the first insulating film 2 and second insulatingfilm 3 are covered with the silicon nitride film 4. Next, the thirdinsulating film 5 is applied to the silicon nitride film 4 surroundinganother conductive section 8 to which another silicon nitride film isapplied. An opening is provided through the third insulating film 5 toform a conductive path extending through the third insulating film 5toward the contact portion 6 a of the conductive section 6 up to thesilicon nitride film 4. An opening is provided through the thirdinsulating film 5 to form a conductive path extending through the thirdinsulating film 5 toward the contact portion 8 a of the conductivesection 8 up to the silicon nitride film 4′. A conductive path isprovided extending from the opening through the silicon nitride film 4and second insulating film 2 to the contact portion 6 a of theconductive section 6. A conductive path is provided extending from theopening through another silicon nitride film 4′ to the contact portion 8a of another conductive section 8.

[0143] In the manufacturing process of a semiconductor device accordingto the foregoing second, fourth, sixth and eighth embodiments, thesilicon nitride film 4 is formed for self-alignment contact in a blanketSiN method in the memory cell array section A, and the silicon nitridefilm 4 is formed simultaneously in the peripheral circuit section B.So-called aluminum contacts are formed by providing conducting leadsfrom the upper layer through the silicon nitride film 4. Morespecifically, in the second and fourth embodiments among theseembodiments, the silicon nitride film 4 is preliminarily removed at theregion for making the aluminum contacts in the peripheral circuitsection B. Then, the interlayer oxide film 5 is applied thereto, andthereafter the conductive paths, i.e., aluminum contacts are formedthrough the interlayer oxide film 5. On the other hand, in the sixth andeighth embodiments, the interlayer oxide film 5 is allied to the siliconnitride film 4 also in the peripheral circuit section B, and then theconductive paths, i.e., aluminum contacts are formed through theinterlayer oxide film 5 and silicon nitride 4.

[0144] Ninth embodiment

[0145]FIG. 19 illustrates a sectional view of the structure of asemiconductor device according to the ninth embodiment of thisinvention. The illustrated semiconductor device (DRAM) is comprised of amemory cell array section A having no aluminum contact, and a peripheralcircuit section B having a substrate, transfer gate, bit line, andaluminum contact on a cell plate. In the drawing, the same referencenumerals as in FIG. 1 designate same or like parts respectively.

[0146] As shown in the drawing, the semiconductor device comprises asemiconductor substrate 1, a first insulating film (oxide film) 2, asecond insulating film (oxide film) 3, a silicon nitride film 4, a thirdinsulating film (interlayer insulating film) 5, a conductive section(transfer gate) 6 and a conductive section (word line) 7 on the firstoxide film 2. Also comprising the device are, a conductive section (bitline) 8 and a conductive section (cell plate) 9 buried at the middleposition in the interlayer insulating film 5, a further conductivesection (bit line) 10 buried at the middle position in the intelayerinsulating film 5, and a contact passage 11 thereof and a thin fifthinsulating film (oxide film) 14.

[0147] The semiconductor substrate 1 has a number of elements formed ona principal plane thereof, and a contact portion 1 a for contactingbetween the layers and a contact portion 1 b for contacting theconductive section 10 are shown herein. The first oxide film 2 isapplied to the principal plan of the semiconductor substrate 1, and isopened at the location through which the bit line contact passage 11extends. The second oxide film 3 is applied to the upper surface of theconductive section 6 and 7. The second oxide film 3 covering the uppersurface of the conductive section 6 has an opening 3 a located at thecontact portion 6 a of the conductive section 6.

[0148] The fifth oxide film 14 is thinly applied to the side surface ofthe conducive sections 6 and 7, and to the side and upper surface of theoxide film 3 thereon. This fifth oxide film 14 is not always essential,and may be omitted.

[0149] The silicon nitride film 4 (SiN) is applied to the first oxidefilm 2 and a fourth oxide film in the memory cell array section A. Onthe other hand, the silicon nitride film 4 is applied only on the risingportion of the fifth oxide film 14 serving as the side faces of theconductive sections 6 and 7 in the peripheral circuit section B havingaluminum contacts. The silicon nitride film 4 is formed for the purposeof self-alignment contact in the memory cell array section A, and issimultaneously formed also in the peripheral section B.

[0150] The intelayer insulating film 5 is applied to the first oxidefilm 2, fifth oxide film 14 and silicon nitride film 4, and has anopening 5 a provided at the contact portion 1 a of the semiconductorsubstrate 1 and an opening 5 b provided at the contact portion 6 a ofthe conductive section 6. Further, an opening 5 c is provided at acontact portion 8 a of the conductive section 8 disposed at a middleposition buried in the interlayer insulating film 5, and an opening 5 dis provided at a contact portion 9 a of the conductive section 9disposed at a middle position.

[0151] The conductive section 6 is formed so as to project from thefirst oxide film 2, and is a conductive part to be a word line servingas a transfer gate. The conductive section 7 is a conductive part to bea gate electrode or word line. The conductive section 8 is a conductivepart serving as a bit line disposed at a middle position buried in theinterlayer insulating film 5 and has a contact portion 8 a.

[0152] The conductive section 9 is a conductive part serving as a cellplate of a capacitor disposed at the middle position buried in theintelayer insulating film 5, and has a contact portion 9 a. Theconductive section 10 is a conductive part serving as a bit line, in thesame manner as the conductive section 8 at another middle positionburied in the interlayer insulating film 5, and has a contact passage 11to the semiconductor substrate 1.

[0153] In the memory cell array section A of this semiconductor device,there are bit line contact passages 11 serving as conductive paths tothe semiconductor substrate 1 and a storage node contact (not shown),and herein a self-alignment technology is utilized.

[0154] On the other hand, in the peripheral circuit section B, there isa bit line contact passage 11 which is formed simultaneously with thebit line contact passage 11 of the memory cell array section A.Furthermore, in the openings 5 a, 5 b, 5 c, 5 d of the interlayerinsulating film 5, the upper metal leads, so-called aluminum contacts,are formed to serve as interlayer conductive paths, extending to thecontact portion 6 a of the conductive section 6, contact portion 8 a ofthe conductive section 8 in the middle position, and contact 9 a of theconductive section 9 in the middle position, respectively.

[0155] In this embodiment of the side wall SiN type self-alignmentmethod, the side wall oxide film 14 of the transfer gate 6 is thinlydisposed, and, in the peripheral circuit section B having aluminumcontacts, the nitride film 4 is left only on the side wall of thetransfer gate 6.

[0156] As a result, any mask to be used may be a rough mask capable ofleaving only in the memory cell array section A. It is easier to performa patterning as compared with the other masks for removing or leavingonly the periphery of the contact. Furthermore, the nitride film 4 usedin self-alignment is removed from all aluminum contacts in theperipheral circuit section B, and thereby the problem of etching stop onthe nitride film is overcome.

[0157] This embodiment may be also restated as follows. That is, in thesemiconductor device according to this embodiment, an insulating filmincluding the insulating films 2, 3 and 5 is applied to thesemiconductor substrate 1 having contact portions on the principalplane, and in this semiconductor film, the conductive section 6 isdisposed near the principal plane of the semiconductor substrate 1 so asto project from the principal plane. Further, in the peripheral circuitsection B, the silicon nitride film 4 is applied to the side face of theconductive section 6. Similarly, another conductive path is providedthrough the insulating film extending to the contact portion 1 a of thesemiconductor substrate 1. In the insulating film, further conductivesections 8 and 9 are disposed, and conductive paths are provided throughthe insulating film extending to the contact portions of the conductivesections.

[0158] Tenth embodiment

[0159] FIGS. 20 to 24 show a manufacturing process of a semiconductordevice according to the tenth embodiment of this invention, and thismanufacturing process is suitable for manufacturing the semiconductordevice of the structure as described in the ninth embodiment. In thedrawings, the same reference numerals as in FIG. 1 or FIG. 2 designatesame or like parts.

[0160] Now the manufacturing process is described. As shown in FIG. 20,a first insulating film (oxide film) 2 is applied to the principal planeof the semiconductor substrate 1. On a part of this first oxide film 2,a conductive section (transfer gate) 6 and a conductive section (wordline) 7 are formed so as to project from the first oxide film 2. Then,upper surfaces of the conductive sections 6 and 7 are further coveredwith a second insulating film (oxide film) 3. The fifth insulating film(oxide film) 14 is applied thinly to the conductive sections 6 and 7 andto the peripheral side face and upper surface of the second oxide film 3thereon.

[0161] A silicon nitride film 4 is applied to the entire surface of thesecond oxide film 2 and the fifth oxide film 14. This silicon nitridefilm 4 is applied to the entire surface of the second oxide film 2 andthe fifth oxide film 14. This silicon nitride film 4 is formed forself-alignment contact in the memory cell array section A, and issimultaneously formed also in the peripheral section B. After coveringthe entire surface with a resist 12, the resist is removed from theperipheral circuit section B wherein aluminum contacts are to be made,while the resist 12 is left in the memory cell array section A.

[0162] Further, as shown in FIG. 21, in the peripheral circuit section Bwhere the resist 12 was removed, the silicon nitride film 4 is left onlyon the side faces of the conductive sections 6 and 7 while being removedby anisotropic etching from the other area. In this manner, theconductive section 7 in the memory cell array section A and theconductive sections 6 and 7 in the peripheral circuit section B areformed respective as shown in FIGS. 24(a) and 24(b).

[0163] Then, as shown in FIG. 22, a third insulating film (silicon oxidefilm serving as an interlayer insulating film) 5 is applied andflattened on the entire surface of the semiconductor substrate 1including the upper surface of the first oxide film 2, silicon nitridefilm 4 and fifth oxide film 14. In this process, an opening is providedthrough the first oxide film 2 on the bit line contact portion 1 b onthe principal plane of he semiconductor substrate 1, and the bit linecontact passage 11 is disposed. Further, the conductive section (bitline) 8 and conductive section (bit line) 10 are disposed at the middleposition in the interlayer oxide film 5. Furthermore, the conductivesection (cell plate) 9 is similarly disposed and buried in theinterlayer oxide film 5. Thereafter, a resist 13 is applied to theentire surface, and openings are provided at the portions where aluminumcontacts are required from above.

[0164] Subsequently, as shown in FIG. 23, the interlayer oxide film 5 isselectively etched from the openings of the resist 13, whereby holes areformed to provide conductive paths to the contact portion 1 a of thesemiconductor substrate 1, the contact portion 6 a of the conductivesection 6, the contact portion 8 a of the word line 8, and the contactportion 9 a of the cell plate 9. Then, the first oxide film 2 on thecontact portion 1 a of the semiconductor substrate 1 and the third oxidefilm 3 and fifth oxide film 14 on the conductive section 6 are etched atthe same time. Thereafter, the resist 13 is removed, and aluminumcontacts serving as conductive paths to the upper parts are formed intheses openings formed in the interlayer oxide film 5.

[0165] Thus, in this embodiment, after forming the conductive section(transfer gate) 6, the thin oxide film 14 and nitride film 4 are formedaccurately (conformably) in the form of gate electrode shape of theconductive section (transfer gate) 6. After patterning the resist 13 inthe memory cell array section A, the nitride film 4 is anisotropicallydry-etched in the peripheral circuit section B. In the anisotropic dryetching, etching takes place only n the perpendicular direction, so thatthe nitride film 4 thick in the longitudinal direction on the sidesurface of the conductive section (transfer gate) 6 is left only as theside wall.

[0166] In this embodiment, any mask to be used for selectively etchingthe silicon nitride film 4 may be a rough mask capable of leaving onlyin the memory cell array section A. It is easier to perform a patterningas compared with the other mask for removing or leaving only at theperiphery of the aluminum contact. Further, the nitride film 4 used inself-alignment is removed from all aluminum contacts n the peripheralcircuit section B, and thereby the problem of etching stop in thenitride film is overcome.

[0167] In this embodiment, furthermore, the area where the siliconnitride film is left in the peripheral circuit section B having aluminumcontact is minimized other than at the memory cell array section A. As aresult of minimizing the silicon nitride film of high dielectricconstant disposed among the leads in the peripheral circuit section Bhaving aluminum contacts there is an advantage that the capacity amongthe leads may be reduced, and the electric characteristics, particularlyoperating speed, may be improved.

[0168] This embodiment may be also restated as follows. That is, in themanufacturing process according to this embodiment, the first insulatingfilm 2 is applied on the principal plan of the semiconductor substrate1, and the conductive section 6 is formed on this first insulating film2. Then the conductive section 6 is covered with the second insulatingfilm 3, and the first insulating film 2 and second insulating film 3,and the first insulating film 3 and second insulating film 3, arecovered with the silicon nitride film 4. A third insulating film 5 isapplied after removing the silicon nitride film 4 while leaving the sameon the side face of the conductive section 6, and openings are providedthrough the third insulating film 5 to form a conductive path extendingthrough the third insulating film 5 to the contact portion 6 a of theconductive section 6 and another conductive path extending to thecontact portion 1 a of the semiconductor substrate 1 respectively.

[0169] Eleventh embodiment

[0170]FIG. 25 illustrates a sectional view of the structure of asemiconductor device according to the eleventh embodiment of thisinvention. The illustrated semiconductor device (DRAM) is comprised of amemory cell array section A having no aluminum contact, and a peripheralcircuit section B having a substrate, transfer gate, bit line, andaluminum contact on a cell plate. In the drawing, same referencenumerals as in FIG. 1 designate same or like parts respectively.

[0171] As shown in the drawing, the semiconductor device comprises asemiconductor substrate 1, a first insulting film (oxide film) 2, asilicon nitride film 4, a third insulating film (interlayer insulatingfilm) 5, a conductive section (transfer gate) 6 and conductive section(word line) 7 on the first oxide film 2, a conductive section (bit line)8 and a conductive section (cell plate) 9 buried at the middle positionin the interlayer insulating film 5, a further conductive section (bitline) 10 buried at the middle position in the interlayer insulating film5, and a contact passage 11 thereof.

[0172] As shown in the drawing, the semiconductor device comprises asemiconductor substrate 1, a first insulating film (oxide film) 2, asecond insulating film (oxide film) 3, a silicon nitride film 4, a thirdinsulating film (interlayer insulating film) 5, a conductive section(transfer gate) 6 and a conductive section (word line) 7 on the firstoxide film 2, a conductive section (bit line) 8 and a conductive section(cell plate) 9 buried at the middle position in the interlayerinsulating film 5, a further conductive section (bit line) 10 buried atthe middle position in the interlayer insulating film 5, and a contactpassage 11 thereof.

[0173] The silicon nitride film (SiN) 4 is formed to cover theconductive sections 6 and 7 on the first oxide film 2. The siliconnitride film 4 covering the conductive section 6 has an opening 4 aprovided at the contact portion 6 a of the conductive section 6. Thissilicon nitride 4 is formed for the purpose of self-alignment contact inthe memory cell array section A and is simultaneously formed also in theperipheral section B.

[0174] The interlayer insulating film 5 is applied to the first oxidefilm 2 and silicon nitride film 4, and has an opening 5 a provided atthe contact portion 1 a of the semiconductor substrate 1 and an opening5 b provided at the contact portion 6 a of the conductive section 6.Further, an opening 5 c is provided at a contact portion 8 a of theconductive section 8 disposed at the middle position and buried in theinterlayer insulating 5, and an opening 5 d is provided at a contactportion 9 a of the conductive section 9.

[0175] The conductive section 6 is formed on a part of the first oxidefilm 2 to project from the first oxide film 2, and is a conductive partto be a word line serving as a transfer gate. The conductive section 7is formed on a part of the first oxide film to project from the firstoxide film 2, and is a conductive part to be a gate electrode or wordline. The conductive section 8 is a conductive part serving as a bitline formed at a middle position in the interlayer insulating film 5with a certain distance from the principal plane of the semiconductorsubstrate 1, and has a contact portio 8 a. The conductive section 9 is aconductive part serving as a cell plate of the capacitor formed at themiddle position in the interlayer insulating film 5 with a certaindistance from the principal plane of the semiconductor substrate 1, andhas a contact portion 9 a. The conductive section 10 is a conductivepart serving as a bit line formed, in the same manner as the conductivesection 8, at another middle position buried in the interlayerinsulating film 5, and has a contact passage 11.

[0176] In the memory cell array section A of this semiconductor device,there are bit line contact passage 11 serving as a conductive path tothe semiconductor substrate 1 and a storage node contact (not shown),and herein a self-alignment technology is utilized.

[0177] On the other hand, in the peripheral circuit section B, there isa bit line contact passage 11 which is formed simultaneously with thebit line contact passage 11 of the memory cell array section A. Further,in the openings 5 a, 5 b, 5 c, 5 d of the interlayer insulating film 5,the upper metal leads, so-called aluminum contacts, are formed to serveas interlayer conductive paths, extending to the contact portion 1 a ofthe semiconductor substrate 1, contact portion 6 a of the conductivesection 6, contact position, and contact portion 9 a of the conductivesection 9 in the middle position, respectively.

[0178] In this embodiment, furthermore, the area where the siliconnitride film is left in the peripheral circuit section B is minimizedexcept the memory cell array section A. As a result of minimizing thesilicon nitride film of high dielectric constant disposed among theleads in the peripheral circuit section B, there is a n advantage suchthat the capacity among the leads may be reduced, and the electriccharacteristics, particularly operating speed, may be improved.

[0179] This embodiment may be also restated as follows. That is, in thesemiconductor device according to this embodiment, an insulating filmincluding the insulating films 2 and 5 applied to the semiconductorsubstrate 1 having contact portions on the principal plane. In thissemiconductor film, the conductive section 6 is disposed near theprincipal plane of the semiconductor substrate 1 and is projecting fromthe principal plane. The silicon nitride film 4 is applied to the uppersurface and side surface of the conductive section 6. Similarly, anotherconductive path is provided through the insulating film 5 extending tothe contact portion 1 a of the semiconductor substrate 1. In theinsulating film, further conductive sections 8 and 9 are disposed, andconductive paths are provided through the insulating film extending tothe contact portions 8 a and 9 a of the conductive sections 8 and 9.

[0180] In the semiconductor device according to the foregoing ninth andeleventh embodiments, the silicon nitride film is formed for theself-alignment contact in a blanket SiN method in the memory cell arraysection A, and the silicon nitride film is formed simultaneously in theperipheral circuit section B through which leads or so-called aluminumcontacts from the upper layer are provided. More specifically, in theninth embodiment, the size of the opening in the silicon nitride film islarger, with sufficient allowance, than the size of the conductivepaths, i.e., than the size of the diameter of the aluminum contactholes. On the other hand, in the eleventh embodiment, the size of theopening of the silicon nitride film is same as the size of theconductive paths, i.e., the size of the diameter of the aluminum contactholes.

[0181] Twelfth embodiment

[0182] FIGS. 26 to 28 show a manufacturing process of a semiconductordevice according to the twelfth embodiment of this invention, and thismanufacturing process is suitable for manufacturing the semiconductordevice of the structure as described in the eleventh embodiment. In thedrawings, the same reference numerals as in FIG. 1 or FIG. 2 designatesame or like parts.

[0183] Now the manufacturing process is described. As shown in FIG. 26,a first insulting film (oxide film) 2 is applied to the principal planeof the semiconductor substrate 1. On a part of this first oxide film 2,a conductive section (transfer gate) 6 and a conductive section (wordline) 7 are formed so as to project from the first oxide film 2. Then, asilicon nitride film 4 is applied over the conductive section startingfrom the oxide film 2 along the surface and covering the conductivesection 6. This process is achieved by applying first the siliconnitride film 4 to the entire surface of the first oxide film 2, andleaving the silicon nitride film 4 only around the conductive sections 6and 7 while removing the silicon nitride film 4 by selective etching inall other parts. This silicon nitride film 4 is formed forself-alignment contact in the memory cell array section A, and issimultaneously formed also in the peripheral section B.

[0184] A third insulating film (silicon oxide film as interlayerinsulating film) 5 is lastly applied to the entire surface of the firstoxide film 2 and silicon nitride film 4. In this process, a bit linecontact passage 11 is provided through the first oxide film 2 to the bitline contact portio 1 b in the principal plane of the semiconductorsubstrate 1. Further, the conductive section (bit line) 8 and conductivesection (bit line) 10 are disposed at the middle position with a certaindistance from the principal plane of the semiconductor substrate 1.Furthermore, the conductive section (cell plate) 9 is buried in theinterlayer oxide film 5.

[0185] Thereafter, a resist 13 is applied, and openings are provided atthe locations of contact portions not covered with the silicon nitridefilm 4, i.e. the contact portion 1 a of the semiconductor substrate 1,contact portion 8 a of the bit line 8 and contact portion 9 a of thecell plate 9. The interlayer oxide film 5 is etched selectively, andthereby openings extending to the contact portions 1 a, 8 a, 9 a areformed.

[0186] Then, as shown in FIG. 27, the openings 5 a, 5 c and 5 dextending to the contact portions 1 a, 8 a and 9 a of the semiconductorsubstrate 1, bit line 8 and cell plate 9 respectively are filed orcovered with the resist 13, and then an opening is formed at thelocation of the contact portio 6 a of the conductive section coveredwith the silicon nitride film 4. Then, the interlayer oxide film 5 isetched selectively, and thereby an opening extending to the siliconnitride 4 is formed.

[0187] Subsequently, as shown in FIG. 28, from the opening 5 b at thelocation of the contact portion 6 a of the conductive section 6, thesilicon nitride film 4 is etched, and thereby an opening reaching to thecontact portion 6 a is formed. Thereafter, the resist 13 is removed, andaluminum contacts are made in the interlayer oxide film 5 to serve asconductive paths to the upper parts through these openings.

[0188] This embodiment shows a manufacturing process in the SiN typeself-alignment method in which the openings for aluminum contacts aremade by etching in two steps using two masks. The process comprises afirst opening step for the contacts on the substrate, bit line and cellplate which do not have a nitride film at the bottom of the opened hole,and second opening step for the contact on the transfer gate which has anitride film at the bottom of the opened hole. In the first step,opening is performed just by dry etching of an oxide film, and in thesecond step, a dry etching of the oxide film is followed by a nitridefilm etching.

[0189] In this manner, since the steps of opening the contact holes areperformed by separate etching for the holes with nitride film andwithout nitride film in the opened hole, it is possible to applydifferent etching specifications. Therefore a reduction in filmthickness of upper leads or penetration of upper leads due toover-etching may be effectively prevented.

[0190] This embodiment may be also restated as follows. That is, in themanufacturing method according to this embodiment, an insulating film 2is applied to the principal of the semiconductor substrate 1, and theconductive section 6 is formed on this insulating film 2. Then, thesilicon nitride film 4 is applied to the conductive section 6, andanother insulating film 5 is applied to the silicon nitride film 4.Next, openings are provided through the insulating film 2 and 5 to forma conductive path extending to the contact portion 1 a of thesemiconductor substrate 1. Then other openings are provided through theinsulating film 5 and silicon nitride film 4 to form a conductive pathextending to the contact portion 6 a of the conductive section 6.

[0191] In the manufacturing process of a semiconductor device accordingto the foregoing tenth and twelfth embodiments, the silicon nitride film4 is formed for self-alignment contact of SiN side wall method in thememory cell array section A, and the silicon nitride film 4 is formedsimultaneously in the peripheral circuit section B, and so-calledaluminum contacts are formed by providing leads from the upper layerthrough the silicon nitride film 4. More specifically, in the tenthembodiment, the silicon nitride film 4 is preliminarily removed at theregion for making the aluminum contracts in the peripheral circuitsection B, and then the interlayer oxide film 5 is applied thereto.Thereafter, the conductive paths, i.e., aluminum contacts are formedthrough the interlayer oxide film 5. On the other hand, in the twelfthembodiment, the interlayer oxide film 5 is applied to the siliconnitride film 4 also in the peripheral circuit section B, and then theconductive paths, i.e., aluminum contacts are formed through theinterlayer oxide film 5 and silicon nitride 4.

[0192] Obviously, many modifications and variations of the presentinvention are possible in light of the above teachings. It is,therefore, to be understood that, within the scope of the appendedclaims, the invention may by practiced otherwise than as specificallydescribed.

1. A semiconductor device comprising: a semiconductor substrate having aplurality of contact portions thereof on a principal plane; aninsulating film applied to the principal plane of said semiconductorsubstrate; a conductive section having a contact portion thereofdisposed in the insulating film near the principal plane of saidsemiconductor substrate; a silicon nitride film disposed in saidinsulating film for covering the principal plane of said semiconductorsubstrate and said conductive section; and a conductive path providedthrough said insulating film and said silicon nitride film and extendingto the contact portion of said conductive section.
 2. A semiconductordevice as set forth in claim 1 , further comprising: a conductive pathprovided through said insulating film and said silicon nitride film andextending to one of the contact portions of said semiconductorsubstrate.
 3. A semiconductor device as set forth in claim 2 , furthercomprising: another conductor having a contact portion thereof disposedin said insulating film; and another conductive path provided throughsaid insulating film and extending to the contact portion of saidanother conductor.
 4. A semiconductor device comprising: a semiconductorsubstrate having a plurality of contact portions thereof on a principalplane; an insulating film applied to the principal plane of saidsemiconductor substrate; a conductive section having a contact portionthereof disposed in the insulating film near the principal plane of saidsemiconductor substrate; a silicon nitride film disposed in theinsulating film at a surrounding area of at least one of the contactportions on the principal plane of said semiconductor substrate andbeing removed in the region of the other contact portions and saidconductive section; a conductor disposed in said insulating film; aconductive path provided through said insulating film and said siliconnitride film and extending from said conductor to the one of the contactportions of said semiconductor substrate; and a conductive path providedthrough said insulating film and extending to the contact portion ofsaid conductive section.
 5. A semiconductor device as set forth in claim4 , further comprising: a conductive path provided through saidinsulating film and extending to the other of the contact portions ofsaid semiconductor substrate.
 6. A semiconductor device as set forth inclaim 5 , further comprising: another conductor having a contact portionthereof disposed in said insulating film; and another conductive pathprovided through said insulating film and extending to the contactportion of said another conductor.
 7. A semiconductor device comprising:a semiconductor substrate having a plurality of contact portions thereofon a principal plane; an insulating film applied to the principal planeof said semiconductor substrate; a conductive section having a contactportion thereof disposed in the insulating film near the principal planeof said semiconductor substrate so as to project from said principalplane; a silicon nitride film disposed on a side surface of saidconductive section in said insulating film; and a conductive pathprovided through said insulating film and extending to the contactportion of said conductive section.
 8. A semiconductor device as setforth in claim 7 , further comprising: a conductive path providedthrough said insulating film and extending to at least one of thecontact portions of said semiconductor substrate.
 9. A semiconductordevice as set forth in claim 8 , further comprising: another conductorhaving a contact portion thereof disposed in said insulating film; andanother conductive path provided through said insulating film andextending to the contact portion of said another conductor.
 10. Asemiconductor device comprising: a semiconductor substrate having aplurality of contact portions thereof on a principal plane; aninsulating film applied to the principal plane of said semiconductorsubstrate; a conductive section having a contact portion thereofdisposed in the insulating film near the principal plane of saidsemiconductor substrate so as to project from said principal plane; asilicon nitride film disposed so as to cover a surface of saidconductive section in said insulating film; and a conductive pathprovided through said insulating film and said silicon nitride film andextending to the contact portion of said conductive section.
 11. Asemiconductor device as set forth in claim 10 , further comprising: aconductive path provided through said insulating film and extending toat least one of the contact portions of said semiconductor substrate.12. A semiconductor device as set forth in claim 11 , furthercomprising: another conductor having a contact portion thereof disposedin said insulating film; and another conductive path provided throughsaid insulating film and extending to the contact portion of saidanother conductor.
 13. A manufacturing process of a semiconductor devicecomprising the steps of: applying a first insulating film to a principalplane of a semiconductor substrate; forming a conductive section havinga contact portion thereof on said first insulating film; applying asecond insulating film to said conductive section; applying a siliconnitride film to said first and second insulating films; removing saidsilicon nitride film at least from a region of the contact portion ofsaid conductive section; covering the whole surface with a thirdinsulating film; and forming a conductive path provided through saidthird insulating film extending to the contact portion of saidconductive section.
 14. A manufacturing process of a semiconductordevice comprising the steps of: applying a first insulating film to aprincipal plane of a semiconductor substrate; forming a conductivesection having a contact portion thereof on said first insulating film;applying a second insulating film to said conductive section; applying asilicon nitride film to said first and second insulating films; removingsaid silicon nitride film leaving it at a predetermined portion of theprincipal plane of said semiconductor substrate; covering the wholesurface with a third insulating film; and forming a conductive paththrough said third insulating film extending to the contact portion ofsaid conductive section.
 15. A manufacturing process of a semiconductordevice comprising the steps of: applying a first insulating film to aprincipal plane of a semiconductor substrate; forming a conductivesection having a contact portion thereof on said first insulating film;covering said conductive section with a second insulating film, applyinga silicon nitride film to said first and second insulating films;removing said silicon nitride film leaving at a side surface of saidconductive section; covering the while surface with a third insulatingfilm; and forming a conductive path provided through said thirdinsulating film extending to the contact portion of said conductivesection.
 16. A manufacturing process of a semiconductor devicecomprising the steps of: applying a first insulating film to a principalplane of a semiconductor substrate; forming a conductive section havinga contact portion thereof on said first insulating film; applying asecond insulating film to said conductive section; applying a siliconnitride film to said first and second insulating films; applying a thirdinsulating film to said silicon nitride film; and forming a conductivepath provided through said third insulating film, said silicon nitridefilm and said second insulating film extending to the contact portion ofsaid conductive section.
 17. A manufacturing process of a semiconductordevice as set forth in claim 16 , further comprising the steps of:embedding a conductor having a contact portion thereof in said thirdinsulating film; and forming a conductive path provided through saidthird insulating film extending to the contact portion of saidconductor.
 18. A manufacturing process of a semiconductor device as setforth in claim 16 , further comprising the steps of: embedding aconductive having a contact portion thereof to which anther siliconnitride film is applied in said third insulating film; and forming aconductive path provided through said third insulating film and saidanother silicon nitride film extending to the contact portion of saidconductor.
 19. A manufacturing process of a semiconductor devicecomprising the steps of: applying an insulating film to a principalplane of a semiconductor substrate having a plurality of contactportions; forming a conductive section having a contact portion thereofon said insulting film; covering said conductive section with a siliconnitride film; covering said silicon nitride film and said insulatingfilm with another insulating film; and forming a conductive pathprovided through said another insulating film and said silicon nitridefilm extending to the contact portion of said conductive section.
 20. Amanufacturing process of a semiconductor device as set forth in claim 19, further comprising a step of: forming a conductive path providedthrough said insulating film and said another insulating film extendingto the contact portion of said semiconductor device.